ca1

1.

1 point

Exploit spatial locality:

None of them

by fetching blocks of data around recently accessed locations

by remembering the contents of recently accessed locations

2.

1 point

What is a ROB?

Recall Buffer

Read Only Buffer

Reorder Buffer

Reload Buffer

3.

1 point

Data Hazard:

Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

An instruction in the pipeline needs a resource being used by another instruction in the pipeline

An instruction depends on a data value produced by an earlier instruction

4.

1 point

What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?

n loop iterations

subroutine call

vector access

5.

1 point

What is a Bandwidth:

a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle

is amount of data that can be in flight at the same time (Little’s Law)

is time for a single access – Main memory latency is usually >> than processor cycle time

6.

1 point

What is kernel process?

Provide at least five modes, indicating whether the running process is a user process or an operating system process

Provide at least two modes, indicating whether the running process is a user process or an operating system process

None of them

Provide a portion of the processor state that a user process can use but not write

7.

1 point

What does DDR stands for?

Double data rate

None of them

Dual data rate

Double data reaction

8.

1 point

Structural Hazard:

Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

An instruction depends on a data value produced by an earlier instruction

An instruction in the pipeline needs a resource being used by another instruction in the pipeline

9.

1 point

Least Recently Used (LRU):

cache state must be updated on every access

Used in highly associative caches

FIFO with exception for most recently used block(s)

10.

1 point

What does DRAM stands for?

Dataram Random Access memory

None of them

Dynamic Random Access memory

Dual Random Access memory

11.

1 point

Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:

none of them

If cache size is doubled, miss rate usually drops by about √2

Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2

12.

1 point

Little’s Law and a series of definitions lead to several useful equations for “Time server” - :

Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

Average time per task in the queue

13.

1 point

Structural Hazard:

Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

An instruction depends on a data value produced by an earlier instruction

An instruction in the pipeline needs a resource being used by another instruction in the pipeline

14.

1 point

How many instructions used in Distributed Superscalar 2 and Exceptions?

4

2

1

3

15.

1 point

Capacity -

misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

first-reference to a block, occur even with infinite cache

16.

1 point

What is Computer Architecture?

is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users

is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies

the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them

17.

1 point

If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:

The time between when the user enters the command and the complete response is displayed

The time from the reception of the response until the user begins to enter the next command

The time for the user to enter the command

18.

1 point

Average Memory Access Time is equal:

Hit Time + ( Miss Rate * Miss Penalty )

Hit Time - ( Miss Rate + Miss Penalty )

Hit Time / ( Miss Rate - Miss Penalty )

Hit Time * ( Miss Rate + Miss Penalty )

19.

1 point

How many issue queue used in Centralized Superscalar 2 and Exceptions?

4

1

3

2

20.

1 point

What does SRAM stands for?

System Random Access memory

Static Random Access memory

Short Random Accessmemory

None of them

21.

1 point

What is a Bandwidth-Delay Product:

is amount of data that can be in flight at the same time (Little’s Law)

is time for a single access – Main memory latency is usually >> than processor cycle time

is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle

22.

1 point

Little’s Law and a series of definitions lead to several useful equations for “Time system” - :

Average time per task in the queue

Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

Average time/task in the system, or the response time, which is the sum of Time queue and Time server

23.

1 point

How many issue queue used in Centralized Superscalar 2 and Exceptions?

2

1

4

3

24.

1 point

Little’s Law and a series of definitions lead to several useful equations for “Length queue” -:

Average number of tasks in service

Average length of queue

25.

1 point

Cache HIT:

No Write Allocate, Write Allocate

Write Through, Write Back

26.

1 point

Conflict -

misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

first-reference to a block, occur even with infinite cache

27.

1 point

What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?

vector access

n loop iterations

subroutine call

28.

1 point

Which of the following formula is true about Issue Queue for “Instruction Ready”:

Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards

Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards

Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards

Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards

29.

1 point

Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:

If cache size is doubled, miss rate usually drops by about √2

None of them

Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2

30.

1 point

Algorithm for Cache HIT:

Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache

Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache

Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache

31.

1 point

Control Hazard:

Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

An instruction in the pipeline needs a resource being used by another instruction in the pipeline

An instruction depends on a data value produced by an earlier instruction

32.

1 point

Little’s Law and a series of definitions lead to several useful equations for “Length server” - :

Average length of queue

Average number of tasks in service

33.

1 point

Exploit temporal locality:

by remembering the contents of recently accessed locations

by fetching blocks of data around recently accessed locations

None of them

34.

1 point

Algorithm for Cache MISS:

Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache

Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache

Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache

35.

1 point

Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :

Average time per task in the queue

Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

36.

1 point

Cache MISS:

No Write Allocate, Write Allocate

Write Through, Write Back

37.

1 point

What is a FSB?

Finished Store Buffer

Finished Stall Buffer

Finished Star Buffer

Finished Stack Buffer

38.

1 point

Cache Hit -

Write Through – write both cache and memory, generally higher traffic but simpler to design

No Write Allocate – only write to main memory

write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated

39.

1 point

Which one is concerning to fallacy?

Simulating enough instructions to get accurate performance measures of the memory hierarchy

Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable

Predicting cache performance of one program from another

Over emphasizing memory bandwidth in DRAMs

40.

1 point

Which one is NOT concerning to pitfall?

Over emphasizing memory bandwidth in DRAMs

Predicting cache performance of one program from another

Simulating enough instructions to get accurate performance measures of the memory hierarchy

Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable

41.

1 point

Compulsory -

cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

first-reference to a block, occur even with infinite cache

42.

1 point

What is a ARF:

Architectural Register File

Architectural Read File

Architecture Reload File

Architecture Relocation File

43.

1 point

What is the access time?

Time between when a read is requested and when the desired word arrives

The minimum time between requests to memory.

None of them

Describes the technology inside the memory chips and those innovative, internal organizations

44.

1 point

What is a Latency:

is amount of data that can be in flight at the same time (Little’s Law)

is time for a single access – Main memory latency is usually >> than processor cycle time

is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle

45.

1 point

The formula of “Iron Law” of Processor Performance:

time/program = instruction/program + cycles/instruction * time/cycle

time/program = instruction/program * cycles/instruction * time/cycle

time/program = instruction/program * cycles/instruction + time/cycle

46.

1 point

If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:

The time between when the user enters the command and the complete response is displayed

The time for the user to enter the command

The time from the reception of the response until the user begins to enter the next command

47.

1 point

Data Hazard:

Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

An instruction depends on a data value produced by an earlier instruction

An instruction in the pipeline needs a resource being used by another instruction in the pipeline

48.

1 point

What is the cycle time?

The maximum time between requests to memory.

The minimum time between requests to memory.

None Of them

Time between when a read is requested and when the desired word arrives

49.

1 point

What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?

n loop operations

subroutine call

vector access

50.

1 point

How many issue queue used in Distributed Superscalar 2 and Exceptions:

3

1

2

4